1. Field of the Invention
The present invention relates to a semiconductor memory device, particularly a dynamic semiconductor memory device (DRAM).
2. Related Background Art
In a related DRAM, a memory cell is composed of an MOS transistor and a capacitor. The scaling-down of the DRAM has been remarkably advanced by the adoption of a trench capacitor structure and a stacked capacitor structure. At present, the cell size of a unit memory cell is scaled down to an area of 2 F×4 F=8 F2, where F is a minimum feature size. Namely, the minimum feature size F decreases with the generation advances, and when the cell size is generally taken to be αF2, a coefficient α also decreases with generational advances. Thus, at the present value of F=0.18 μm, α=8 is realized.
In order to hereafter secure the trend of cell size or chip size which is the same as before, it is demanded to satisfy α<8 in F<0.18 μm and further satisfy α<6 in F<0.13 μm, and together with microfabrication, the formation of a cell size of a possible small area becomes a large problem. Accordingly, various proposals for decreasing the size of a single memory cell with a single transistor and a single capacitor to 6 F2 or 4 F2 are made. However, practical use is not easy since there are technical difficulties that the transistor has to be of a vertical type, and that electric interference between adjacent memory cells increases, and in addition difficulties in terms of manufacturing technology including fabrication, film formation, and the like.
On the other hand, some proposals for a DRAM in which a memory cell is composed of one transistor without using a capacitor are made as mentioned below.
(1) JOHN E. LEISS et al, “dRAM Design Using the Taper-Isolated Dynamic Cell” (IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. ED-29, NO. 4, APRIL 1982, pp 707-714)
(2) Japanese Patent Laid-open Publication No. H3-171768
(3) Marnix R. Tack et al, “The Multistable Charge-Controlled Memory Effect in SOI MOS Transistors at Low Temperatures” (IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL, 37, MAY, 1990, pp 1373-1382)
(4) Hsing-jen Wann et al, “A Capacitorless DRAM Cell on SOI Substrate” (IEDM93, pp 635-638)
A memory cell in (1) is composed of MOS transistors, each of which has a buried channel structure. Charge and discharge to/from a surface inversion layer is performed using a parasitic transistor formed at a taper portion of an element isolation insulating film to perform binary storage.
A memory cell in (2) uses MOS transistors which are well-isolated from each other and uses a threshold voltage of the MOS transistor fixed by a well potential as binary data.
A memory cell in (3) is composed of MOS transistors on an SOI substrate. A large negative voltage is applied from the SOI substrate side, and by utilizing accumulation of holes in an oxide film of a silicon layer and an interface, binary storage is performed by emitting and injecting these holes.
A memory cell in (4) is composed of MOS transistors on an SOI substrate. The MOS transistor is one in terms of structure, but here a structure is adopted, in which a reverse conduction-type layer is formed on top of the surface of a drain diffusion region, whereby a P-MOS transistor for write and an N-MOS transistor for read are substantially combined integrally. With a substrate region of the N-MOS transistor as a floating node, binary data are stored by its potential.
However, in (1), the structure is complicated and the parasitic transistor is used, whereby there is a disadvantage in the controllability of its characteristic. In (2), the structure is simple, but it is necessary to control potential by connecting both a drain and a source of the transistor to a signal line. Moreover, the cell size is large, and rewriting bit by bit is impossible because of the well isolation. In (3), a potential control from the SOI substrate side is needed, and hence rewriting bit by bit is impossible, whereby there is a difficulty in controllability. In (4), a special transistor structure is needed, and the memory cell requires a word line, a write bit line, a read bit line, and a purge line, whereby the number of signal lines increases.